Intel die sizes: Coffee Lake, Comet Lake, and Ice Lake

Intel, for whatever reason, has seen fit to stop publishing die sizes and transistor counts (estimates) on it's latest CPUs. It's a strange move, probably driven by the company's difficulties with getting high-end 10nm parts out the door. Sure, Ice Lake now exists and is readily available, but 10nm was at least three years late. But I digress.

I really just wanted to gather all the die size information I had into one place, for ease of reference. Transistor counts could be estimated, but the density varies depending on what sort of logic is in use (cache, branch predictor, etc.) so I'm not going to even try. But here are the current die sizes, based on physical chip measurements (which are accurate to within probably 2%):

These first three come courtesy of der8auer, who routinely delids CPUs. (Links to Amazon earn me affiliate commissions.)

Core i7-8700K die size: 9.2 x 16.7 mm ~= 153.6 mm2

Core i9-9900K die size: 9.2 x 19.6 mm ~= 180.3 mm2

Core i9-10900K die size: 9.2 x 22.4 mm ~= 206.1 mm2

What about Ice Lake? As with recent Intel U-series processors, the package has two chips. The smaller is the platform controller hub (PCH) while the larger represents the main Ice Lake CPU. I've seen earlier estimates based on the Ice Lake wafer that the die size was around 130 mm2. However, using the package shots it's actually smaller than that.

Ice Lake / Core i7-1065G7 die size: 11.40 x 10.78 mm ~= 122.9 mm2

Ice Lake PCH die size: 5.74 x 9.42 mm ~= 54.1 mm2

Intel does have plans to release server variants of Ice Lake, which presumably means yields are good enough that it can actually manufacture larger chips. But how big would such a chip be?

The current 123 mm2 Ice Lake chips have a rather large GPU cluster that wouldn't be needed for servers. In fact, the 4-core CPU cluster only occupies about a quarter of the entire die space right now, with other portions used for the DDR4 memory controller, system agent, and GPU.

To be more precise, the CPU cores and ring bus use about 26.5% of the die area. The Gen11 graphics is about one third (33.6%) of the die space, the DDR4 controller is only 6.3% of the die, and the system agent makes up the remaining 33.6% of the die.

So if Intel wanted to make, for example, a 32-core Ice Lake server part using the same size Sunny Cove cores, with an 8-channel memory interface, it wouldn't even need to be that big of a chip. Oh, it would be much larger than the current Ice Lake-U CPU+GPU's 123 mm2, but as a rough estimate, Intel could do 32-core Ice Lake with a die size of about 375 mm2. Piece of cake! And only two years late compared to the competition.